VHDL And Port

library ieee;
use ieee.std_logic_1164.all;

entity AndPort is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);

architecture DataFlow of AndPort is
begin

F <= x and y;

end DataFlow;

architecture DataFlow2 of AndPort is
begin

process(x,y)
begin
if ((x='1') and (y='1')) then
F<= '1';
else
F <='0';
end if;
end process;
end DataFlow2;