VHDL code for Correct Clock (For instance UART Clock)

The next VHDL sample code shows you how to get an UART clock out of an 50Mhz clock (for i nstance on your Xilinx board). For getting 38,4Khz out of 50Mhz we have to divide the frequency by 130. 130 is in hexadecimal format 82. So in my VHDL code you see X"82" this means 130 in decimal format.

library IEEE;
use IEEE.std_logic_1164.all;

entity UART_CLK is
port(
clk: in std_logic;
rst: in std_logic;
CLK384: out std_logic
);
end UART_CLK;

architecture behav of UART_CLK is
signal clkDiv: std_logic_vector(7 downto 0);
signal CLKt: std_ulogic;
constant baudDivide: std_logic_vector (7 downto 0) :=X"82";

begin

process(clk,rst)
begin
if (rst='1') then
clkDiv <= baudDivide;
CLKt<='0';
elseif (clk='1' and clk'event) then
if (clkDiv=X"00") then
clkDiv<=baudDivide;
CLKt <=not CLKt;
else
clkDiv <=clkDiv -1;
end if;
end if
end process;
CLK384 <=CLKt;
end behav;