VHDL code for 2 input NAND gate

library ieee;
use ieee.std_logic_1164.all;

entity NANDGATE2 is port(
x: in std_logic;
y: in std_logic;
f: out std_logic);
end NANDGATE2;

architecture behav of NANDGATE2 is
begin
f<= x NAND y;
end behav;