VHDL code for 3 input NOR gate

library IEEE;
use IEEE.std_logic_1164.all;

entity NORGATE3 is port(
x: in std_logic;
y: in std_logic;
z: in std_logic;
f: out std_logic);
end NORGATE3;

architecture behav of NORGATE3 is
signal xory, xoryorz:std_logic;
begin
xory<= x OR y;
xoryorz <= xory OR z;
f<= NOT xoryorz;

end behav;