VHDL code for a Function

This example shows the VHDL code that you can use if you want to implement a function:
f= (xy'z)+(xyz')+(xyz)

library IEEE;
use ieee.std_logic_1164.all;

entity FUNCTIONEXAMPLE is port(
x: in std_logic;
y:in std_logic;
z: in std_logic;
f: out std_logic;
end FUNCTIONEXAMPLE;

architecture behav of FUNCTIONEXAMPLE is
signal term_1, term_2, term_3: std_logic;
begin
term_1 <= x AND (NOT y) AND z;
term_2 <= x AND y AND (NOT z);
term_3 <= x AND y AND z;
f <= term_1 OR term_2 OR term_3;
end behav;