VHDL Code for a 2:1 MUX

library IEEE;
use ieee.std_logic_1164.all;

ENTITY Mux2x1 IS {
PORT (a0, a1, sel: IN BIT; z: OUT BIT); }
END Mux2x1;

ARCHITECTURE conditional OF Mux2x1 IS
BEGIN
z <= a0 WHEN sel = ‘0’ ELSE a1;
END conditional;