VHDL Code for a 4-bit Ripple Carry

library IEEE;
use ieee.std_logic_1164.all;

ENTITY RCA4 IS PORT(
a, b: IN BIT_VECTOR(3 DOWNTO 0);
cin: IN BIT;
z: OUT BIT_VECTOR(3 DOWNTO 0);
cout: OUT BIT);
END RCA4;


ARCHITECTURE iterative OF RCA4 IS
SIGNAL cm: BIT_VECTOR(0 TO 3);
BEGIN
g_main: FOR k IN 0 TO 3 GENERATE
g_first: IF k = 0 GENERATE
c0: FA PORT MAP (a(k),b(k), cin, z(k), cm(k));
END GENERATE;
g_other: IF k > 0 GENERATE
co: FA PORT MAP (a(k), b(k), cm(k-1), z(k), cm(k));
END GENERATE;
END GENERATE;
cout <= cm(3);
END iterative;