VHDL Code for a 4:1 MUX (Using Entity)

library IEEE;
use ieee.std_logic_1164.all;

ENTITY Mux4x1 IS PORT (
a : IN BIT_VECTOR(3 DOWNTO 0);
sel: IN BIT_VECTOR(0 TO 1) ;
z: OUT BIT); }
END Mux4x1;

ARCHITECTURE mux2x1_based OF Mux4x1 IS
SIGNAL im0, im1 : BIT;
BEGIN
m1: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(0), a(1), sel(0), im0);
m2: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(2), a(3), sel(0), im1);
m3: ENTITY WORK.Mux2x1(selected) PORT MAP (im0, im1, sel(1), z);
END mux2x1_based;