VHDL Code for an infinite Process
library IEEE;
use ieee.std_logic_1164.all;
PROCESS
BEGIN
x <= ‘0’, a AFTER 10 ns, b AFTER 35 ns;
y <= a AND b AFTER 15 ns;
END PROCESS;
posted by VHDL.EU @ 10:43 AM
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Massive listing of VHDL code used in FPGA's of the different FPGA manufacturers. (Xilinx, Actel , Altera,...). You can also download VHDL code of softcores on this blog.
Friday, September 29, 2006
use ieee.std_logic_1164.all;
PROCESS
BEGIN
x <= ‘0’, a AFTER 10 ns, b AFTER 35 ns;
y <= a AND b AFTER 15 ns;
END PROCESS;
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