VHDL Code for 3 INPUT AND PORT
-- TryOUT1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TryOut1 is
port(
X: in std_logic;
Y: in std_logic;
Z: in std_logic;
A: out std_logic);
end TryOut1;
architecture behaviour of TryOut1 is
begin
process(X,Y,Z)
begin
A<= X and Y and Z;
end process;
end behaviour;
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