VHDL Code for a 1 to 4 Demultiplexer

-- TryOUT1.vhd
-- Created by Vincent Claes
-- check out http://www.fpga.be

library ieee;
use ieee.std_logic_1164.all;

entity TryDeMUX is
port( X: in std_logic;
sel: in std_logic_vector (1 downto 0);
A: out std_logic;
B: out std_logic;
C: out std_logic;
D: out std_logic);
end TryDeMUX;

architecture behaviour of TryDeMUX is
begin
process(sel,X)
begin
case sel is
when "00"=>
A <=X;
B <= '0';
C <= '0';
D <= '0';
when "01" =>
B <=X;
A <='0';
C <='0';
D <='0';
when "10" =>
C <=X;
A <='0';
B <='0';
D <='0';
when others =>
D <=X;
A <='0';
B <= '0';
C <='0';
end case;
end process;
end behaviour;