VHDL code for alternative 2 to 1 MUX

-- TryOUT1.vhd
library ieee;
use ieee.std_logic_1164.all;

entity TryMUX is
port(
X: in std_logic;
Y: in std_logic;
Z: in std_logic;
A: out std_logic);
end TryMUX;

architecture behaviour of TryMUX is
begin
process(Z)
begin
if(Z='0')
then
A<=X;
else
A<=Y;
end if;
end process;
end behaviour;