VHDL Code for Adder with Carry!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ADD is
generic(n: natural :=2);
port(
A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end ADD;

architecture behav of ADD is

signal res: std_logic_vector(n downto 0);
begin
res <= ('0' & A)+('0' & B);
sum <= res(n-1 downto 0);
carry <= res(n);
end behav;