VHDL Code for Alternative Full Adder

Library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder is port (
CarryIn, Xin, Yin: in std_logic;
CarryOut,SumOut: out std_logic);
end fulladder;

architecture behav of fa is
begin
CarryOut <= (Xin and Yin) or (CarryIn and (Xin xor Yin));
SumOut <= Xin xor Yin xor CarryIn;
end behav;