VHDL Code for Ripple Carry Adder

For this example you must use the code of the FullAdder below and maybe make some changes...

library IEEE;
use ieee.std_logic_1164.all;

entity Add4 is port (
A,B: in std_logic_vector(3 downto 0);
CarryOut: out std_logic;
Add4: out std_logic_vector(3 downto0));
end Add4;

architecture Struct of Add4 is
component FullAdder port (
ci,xi,yi: in std_logic;
co, si: out std_logic);
end component;

signal Carryv: std_logic_vector(4 downto 0);

begin
Carryv(0) <'0';

Adder: For k In 3 dowto 0 Generate
FullAdder: FA PORT MAP (Carryv(k),A(k),B(k),Carryv(k+1),SUM(k));
End generate Adder;

Cout <= Carryv(4);
End Struct;