Basic VHDL Code for 74381 IC

-- IC74381.vhd
-- Code is not finished yet...

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity IC74381 is port( A: in std_logic_vector (3 downto 0);
B: in std_logic_vector (3 downto 0);
S: in std_logic_vector (2 downto 0);
F: out std_logic_vector(7 downto 0) );
end entity;

architecture behav of IC74381 is
-- S: 0 0 0 for clear operation
-- S: 0 0 1 B minus A
-- S: 0 1 0 A minus B
-- S: 0 1 1 A plus B
-- S: 1 0 0 (notA and B) or (A and not B)
-- S: 1 0 1 A or B -- S: 1 1 0 A and B
-- S: 1 1 1 preset begin process(A,B,S)
begin
case S is
when "000" => F <= "00000000";
when "001" => F <= "0000"& B-A;
when "010" => F <= "0000"& A-B;
when "011" => F <= "0000"& A+B;
when "100" => F <= "0000"&(((not A) and B) or (A and (not B)));
when "101" => F <= "0000"& (A or B);
when "110" => F <= "0000"& (A and B);
when "111" => F <= "11111111";
end case;
end process;
end behav;