VHDL Or Port

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity OrPort is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);

architecture DataFlow of OrPort is
begin

F<= x or y;

end DataFlow;

architecture DataFlow2 of OrPort is
begin

process(x,y)
begin
if((x='1') or (y='1')) then
F <='1';
else
F<='0';
end if;
end process;

end DataFlow2;