VHDL Code for Ripple Carry Adder

For this example you must use the code of the FullAdder below and maybe make some changes...

library IEEE;
use ieee.std_logic_1164.all;

entity Add4 is port (
A,B: in std_logic_vector(3 downto 0);
CarryOut: out std_logic;
Add4: out std_logic_vector(3 downto0));
end Add4;

architecture Struct of Add4 is
component FullAdder port (
ci,xi,yi: in std_logic;
co, si: out std_logic);
end component;

signal Carryv: std_logic_vector(4 downto 0);

begin
Carryv(0) <'0';

Adder: For k In 3 dowto 0 Generate
FullAdder: FA PORT MAP (Carryv(k),A(k),B(k),Carryv(k+1),SUM(k));
End generate Adder;

Cout <= Carryv(4);
End Struct;

VHDL Code for Alternative Full Adder

Library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder is port (
CarryIn, Xin, Yin: in std_logic;
CarryOut,SumOut: out std_logic);
end fulladder;

architecture behav of fa is
begin
CarryOut <= (Xin and Yin) or (CarryIn and (Xin xor Yin));
SumOut <= Xin xor Yin xor CarryIn;
end behav;

VHDL Code for Adder with Carry!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ADD is
generic(n: natural :=2);
port(
A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end ADD;

architecture behav of ADD is

signal res: std_logic_vector(n downto 0);
begin
res <= ('0' & A)+('0' & B);
sum <= res(n-1 downto 0);
carry <= res(n);
end behav;

VHDL Code for a 1 to 4 Demultiplexer

-- TryOUT1.vhd
-- Created by Vincent Claes
-- check out http://www.fpga.be

library ieee;
use ieee.std_logic_1164.all;

entity TryDeMUX is
port( X: in std_logic;
sel: in std_logic_vector (1 downto 0);
A: out std_logic;
B: out std_logic;
C: out std_logic;
D: out std_logic);
end TryDeMUX;

architecture behaviour of TryDeMUX is
begin
process(sel,X)
begin
case sel is
when "00"=>
A <=X;
B <= '0';
C <= '0';
D <= '0';
when "01" =>
B <=X;
A <='0';
C <='0';
D <='0';
when "10" =>
C <=X;
A <='0';
B <='0';
D <='0';
when others =>
D <=X;
A <='0';
B <= '0';
C <='0';
end case;
end process;
end behaviour;

VHDL code for alternative 2 to 1 MUX

-- TryOUT1.vhd
library ieee;
use ieee.std_logic_1164.all;

entity TryMUX is
port(
X: in std_logic;
Y: in std_logic;
Z: in std_logic;
A: out std_logic);
end TryMUX;

architecture behaviour of TryMUX is
begin
process(Z)
begin
if(Z='0')
then
A<=X;
else
A<=Y;
end if;
end process;
end behaviour;

VHDL Code for 3 INPUT AND PORT

-- TryOUT1.vhd
library ieee;
use ieee.std_logic_1164.all;

entity TryOut1 is
port(
X: in std_logic;
Y: in std_logic;
Z: in std_logic;
A: out std_logic);
end TryOut1;

architecture behaviour of TryOut1 is
begin
process(X,Y,Z)
begin
A<= X and Y and Z;
end process;
end behaviour;

VHDL Code that connects an input to an output

-- DRIVER.vhd

library ieee;

use ieee.std_logic_1164.all;

entity Driver is

port( x: in std_logic;

F: out std_logic

);

end Driver;

architecture behv1 of Driver is

begin
process(x)

begin

-- compare to truth table

if (x='1') then

F <= '1';

else

F <= '0';

end if;

end process;
end behv1;

architecture behv2 of Driver is

begin
F <= x;
end behv2;