VHDL code for a Function

This example shows the VHDL code that you can use if you want to implement a function:
f= (xy'z)+(xyz')+(xyz)

library IEEE;
use ieee.std_logic_1164.all;

entity FUNCTIONEXAMPLE is port(
x: in std_logic;
y:in std_logic;
z: in std_logic;
f: out std_logic;
end FUNCTIONEXAMPLE;

architecture behav of FUNCTIONEXAMPLE is
signal term_1, term_2, term_3: std_logic;
begin
term_1 <= x AND (NOT y) AND z;
term_2 <= x AND y AND (NOT z);
term_3 <= x AND y AND z;
f <= term_1 OR term_2 OR term_3;
end behav;

VHDL code for 3 input NOR gate

library IEEE;
use IEEE.std_logic_1164.all;

entity NORGATE3 is port(
x: in std_logic;
y: in std_logic;
z: in std_logic;
f: out std_logic);
end NORGATE3;

architecture behav of NORGATE3 is
signal xory, xoryorz:std_logic;
begin
xory<= x OR y;
xoryorz <= xory OR z;
f<= NOT xoryorz;

end behav;

VHDL code for 2 input NAND gate

library ieee;
use ieee.std_logic_1164.all;

entity NANDGATE2 is port(
x: in std_logic;
y: in std_logic;
f: out std_logic);
end NANDGATE2;

architecture behav of NANDGATE2 is
begin
f<= x NAND y;
end behav;

VHDL code for Correct Clock (For instance UART Clock)

The next VHDL sample code shows you how to get an UART clock out of an 50Mhz clock (for i nstance on your Xilinx board). For getting 38,4Khz out of 50Mhz we have to divide the frequency by 130. 130 is in hexadecimal format 82. So in my VHDL code you see X"82" this means 130 in decimal format.

library IEEE;
use IEEE.std_logic_1164.all;

entity UART_CLK is
port(
clk: in std_logic;
rst: in std_logic;
CLK384: out std_logic
);
end UART_CLK;

architecture behav of UART_CLK is
signal clkDiv: std_logic_vector(7 downto 0);
signal CLKt: std_ulogic;
constant baudDivide: std_logic_vector (7 downto 0) :=X"82";

begin

process(clk,rst)
begin
if (rst='1') then
clkDiv <= baudDivide;
CLKt<='0';
elseif (clk='1' and clk'event) then
if (clkDiv=X"00") then
clkDiv<=baudDivide;
CLKt <=not CLKt;
else
clkDiv <=clkDiv -1;
end if;
end if
end process;
CLK384 <=CLKt;
end behav;

VHDL code for Rising edge D Flip-Flop with Asynchronous Reset

library IEEE;
use IEEE.std_logic_1164.all;

entity dff_async_rst is
port ( data, clk, reset: in std_logic;
q: out std_logic);
end dff_async_rst;

architecture behav of dff_async_rst is
begin
process (clk, reset) begin
if (reset = '0') then
q<='0';
elsif (clk'event and clk='1') then
q<= data;
end if;
end process
end behav;

VHDL code for Rising edge D Flip-Flop

library IEEE;
use IEEE.std_logic_1164.all;

entity dff is
port ( data,clk,: in std_logic;
q: out std_logic);
end dff;

architecture behav of dff is
begin
process (clk) begin
if (clk'event and clk='1') then
q <= data;
end if;
end process;
end behav;

VHDL reserved keywords

The following is a list of the VHDL reserved keywords:

• abs
• access
• after
• alias
• all
• and
• architecture
• array
• assert
• attribute
• begin
• block
• body
• buffer
• bus
• case
• component
• configuration
• constant
• disconnect
• downto
• else
• elsif
• end
• entity
• exit
• file
• for
• function
• generate
• generic
• group
• guarded
• if
• impure
• in
• inertial
• inout
• is
• label
• library
• linkage
• literal
• loop
• map
• mod
• nand
• new
• next
• nor
• not
• null
• of
• on
• open
• or
• others
• out
• package
• port
• postponed
• procedure
• process
• pure
• range
• record
• register
• reject
• rem
• report
• return
• rol
• ror
• select
• severity
• shared
• signal
• sla
• sra
• srl
• subtype
• then
• to
• transport
• type
• unaffected
• units
• until
• use
• variable
• wait
• when
• while
• with
• xnor
• xor