VHDL Code for an infinite Process

library IEEE;
use ieee.std_logic_1164.all;

PROCESS
BEGIN
x <= ‘0’, a AFTER 10 ns, b AFTER 35 ns;
y <= a AND b AFTER 15 ns;
END PROCESS;

VHDL Code for a 4-bit Ripple Carry

library IEEE;
use ieee.std_logic_1164.all;

ENTITY RCA4 IS PORT(
a, b: IN BIT_VECTOR(3 DOWNTO 0);
cin: IN BIT;
z: OUT BIT_VECTOR(3 DOWNTO 0);
cout: OUT BIT);
END RCA4;


ARCHITECTURE iterative OF RCA4 IS
SIGNAL cm: BIT_VECTOR(0 TO 3);
BEGIN
g_main: FOR k IN 0 TO 3 GENERATE
g_first: IF k = 0 GENERATE
c0: FA PORT MAP (a(k),b(k), cin, z(k), cm(k));
END GENERATE;
g_other: IF k > 0 GENERATE
co: FA PORT MAP (a(k), b(k), cm(k-1), z(k), cm(k));
END GENERATE;
END GENERATE;
cout <= cm(3);
END iterative;

VHDL Code for a 4:1 MUX (Using Entity)

library IEEE;
use ieee.std_logic_1164.all;

ENTITY Mux4x1 IS PORT (
a : IN BIT_VECTOR(3 DOWNTO 0);
sel: IN BIT_VECTOR(0 TO 1) ;
z: OUT BIT); }
END Mux4x1;

ARCHITECTURE mux2x1_based OF Mux4x1 IS
SIGNAL im0, im1 : BIT;
BEGIN
m1: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(0), a(1), sel(0), im0);
m2: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(2), a(3), sel(0), im1);
m3: ENTITY WORK.Mux2x1(selected) PORT MAP (im0, im1, sel(1), z);
END mux2x1_based;

VHDL Code for a 2:1 MUX

library IEEE;
use ieee.std_logic_1164.all;

ENTITY Mux2x1 IS {
PORT (a0, a1, sel: IN BIT; z: OUT BIT); }
END Mux2x1;

ARCHITECTURE conditional OF Mux2x1 IS
BEGIN
z <= a0 WHEN sel = ‘0’ ELSE a1;
END conditional;