Combinatoric Logic in VHDL example

-- IMEC_TSO_OEF1.vhd
-- Vincent Claes
-- FPGA.BE

library IEEE;
use ieee.std_logic_1164.all;

entity combvb is
port (
a: in std_logic_vector(3 downto 0);
b: in std_logic;
c: in std_logic;
sel: in std_logic;
uit: out std_logic );

end combvb;

architecture logica of combvb is
signal en_a : std_logic;
signal exor_bc: std_logic;

begin
exor: process(b,c)
begin
if b/=c then
exor_bc <='1';
else
exor_bc <='0';
end if;
end process;

en: process(a)
begin
en_a <= a(0) and a(1) and a(2) and a(3);
end process;

multiplexer: process(en_a,exor_bc,sel)
begin
case sel is
when '0' => uit <=en_a;
when others => uit <=exor_bc;
end case;
end process;

end architecture logica;