Combinatoric Logic in VHDL example

-- IMEC_TSO_OEF1.vhd
-- Vincent Claes
-- FPGA.BE

library IEEE;
use ieee.std_logic_1164.all;

entity combvb is
port (
a: in std_logic_vector(3 downto 0);
b: in std_logic;
c: in std_logic;
sel: in std_logic;
uit: out std_logic );

end combvb;

architecture logica of combvb is
signal en_a : std_logic;
signal exor_bc: std_logic;

begin
exor: process(b,c)
begin
if b/=c then
exor_bc <='1';
else
exor_bc <='0';
end if;
end process;

en: process(a)
begin
en_a <= a(0) and a(1) and a(2) and a(3);
end process;

multiplexer: process(en_a,exor_bc,sel)
begin
case sel is
when '0' => uit <=en_a;
when others => uit <=exor_bc;
end case;
end process;

end architecture logica;

Basic VHDL Code for 74381 IC

-- IC74381.vhd
-- Code is not finished yet...

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity IC74381 is port( A: in std_logic_vector (3 downto 0);
B: in std_logic_vector (3 downto 0);
S: in std_logic_vector (2 downto 0);
F: out std_logic_vector(7 downto 0) );
end entity;

architecture behav of IC74381 is
-- S: 0 0 0 for clear operation
-- S: 0 0 1 B minus A
-- S: 0 1 0 A minus B
-- S: 0 1 1 A plus B
-- S: 1 0 0 (notA and B) or (A and not B)
-- S: 1 0 1 A or B -- S: 1 1 0 A and B
-- S: 1 1 1 preset begin process(A,B,S)
begin
case S is
when "000" => F <= "00000000";
when "001" => F <= "0000"& B-A;
when "010" => F <= "0000"& A-B;
when "011" => F <= "0000"& A+B;
when "100" => F <= "0000"&(((not A) and B) or (A and (not B)));
when "101" => F <= "0000"& (A or B);
when "110" => F <= "0000"& (A and B);
when "111" => F <= "11111111";
end case;
end process;
end behav;

VHDL Code for Ripple Carry Adder

For this example you must use the code of the FullAdder below and maybe make some changes...

library IEEE;
use ieee.std_logic_1164.all;

entity Add4 is port (
A,B: in std_logic_vector(3 downto 0);
CarryOut: out std_logic;
Add4: out std_logic_vector(3 downto0));
end Add4;

architecture Struct of Add4 is
component FullAdder port (
ci,xi,yi: in std_logic;
co, si: out std_logic);
end component;

signal Carryv: std_logic_vector(4 downto 0);

begin
Carryv(0) <'0';

Adder: For k In 3 dowto 0 Generate
FullAdder: FA PORT MAP (Carryv(k),A(k),B(k),Carryv(k+1),SUM(k));
End generate Adder;

Cout <= Carryv(4);
End Struct;

VHDL Code for Alternative Full Adder

Library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder is port (
CarryIn, Xin, Yin: in std_logic;
CarryOut,SumOut: out std_logic);
end fulladder;

architecture behav of fa is
begin
CarryOut <= (Xin and Yin) or (CarryIn and (Xin xor Yin));
SumOut <= Xin xor Yin xor CarryIn;
end behav;

VHDL Code for Adder with Carry!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ADD is
generic(n: natural :=2);
port(
A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);
end ADD;

architecture behav of ADD is

signal res: std_logic_vector(n downto 0);
begin
res <= ('0' & A)+('0' & B);
sum <= res(n-1 downto 0);
carry <= res(n);
end behav;

VHDL Code for a 1 to 4 Demultiplexer

-- TryOUT1.vhd
-- Created by Vincent Claes
-- check out http://www.fpga.be

library ieee;
use ieee.std_logic_1164.all;

entity TryDeMUX is
port( X: in std_logic;
sel: in std_logic_vector (1 downto 0);
A: out std_logic;
B: out std_logic;
C: out std_logic;
D: out std_logic);
end TryDeMUX;

architecture behaviour of TryDeMUX is
begin
process(sel,X)
begin
case sel is
when "00"=>
A <=X;
B <= '0';
C <= '0';
D <= '0';
when "01" =>
B <=X;
A <='0';
C <='0';
D <='0';
when "10" =>
C <=X;
A <='0';
B <='0';
D <='0';
when others =>
D <=X;
A <='0';
B <= '0';
C <='0';
end case;
end process;
end behaviour;

VHDL code for alternative 2 to 1 MUX

-- TryOUT1.vhd
library ieee;
use ieee.std_logic_1164.all;

entity TryMUX is
port(
X: in std_logic;
Y: in std_logic;
Z: in std_logic;
A: out std_logic);
end TryMUX;

architecture behaviour of TryMUX is
begin
process(Z)
begin
if(Z='0')
then
A<=X;
else
A<=Y;
end if;
end process;
end behaviour;

VHDL Code for 3 INPUT AND PORT

-- TryOUT1.vhd
library ieee;
use ieee.std_logic_1164.all;

entity TryOut1 is
port(
X: in std_logic;
Y: in std_logic;
Z: in std_logic;
A: out std_logic);
end TryOut1;

architecture behaviour of TryOut1 is
begin
process(X,Y,Z)
begin
A<= X and Y and Z;
end process;
end behaviour;

VHDL Code that connects an input to an output

-- DRIVER.vhd

library ieee;

use ieee.std_logic_1164.all;

entity Driver is

port( x: in std_logic;

F: out std_logic

);

end Driver;

architecture behv1 of Driver is

begin
process(x)

begin

-- compare to truth table

if (x='1') then

F <= '1';

else

F <= '0';

end if;

end process;
end behv1;

architecture behv2 of Driver is

begin
F <= x;
end behv2;

VHDL Code for an infinite Process

library IEEE;
use ieee.std_logic_1164.all;

PROCESS
BEGIN
x <= ‘0’, a AFTER 10 ns, b AFTER 35 ns;
y <= a AND b AFTER 15 ns;
END PROCESS;

VHDL Code for a 4-bit Ripple Carry

library IEEE;
use ieee.std_logic_1164.all;

ENTITY RCA4 IS PORT(
a, b: IN BIT_VECTOR(3 DOWNTO 0);
cin: IN BIT;
z: OUT BIT_VECTOR(3 DOWNTO 0);
cout: OUT BIT);
END RCA4;


ARCHITECTURE iterative OF RCA4 IS
SIGNAL cm: BIT_VECTOR(0 TO 3);
BEGIN
g_main: FOR k IN 0 TO 3 GENERATE
g_first: IF k = 0 GENERATE
c0: FA PORT MAP (a(k),b(k), cin, z(k), cm(k));
END GENERATE;
g_other: IF k > 0 GENERATE
co: FA PORT MAP (a(k), b(k), cm(k-1), z(k), cm(k));
END GENERATE;
END GENERATE;
cout <= cm(3);
END iterative;

VHDL Code for a 4:1 MUX (Using Entity)

library IEEE;
use ieee.std_logic_1164.all;

ENTITY Mux4x1 IS PORT (
a : IN BIT_VECTOR(3 DOWNTO 0);
sel: IN BIT_VECTOR(0 TO 1) ;
z: OUT BIT); }
END Mux4x1;

ARCHITECTURE mux2x1_based OF Mux4x1 IS
SIGNAL im0, im1 : BIT;
BEGIN
m1: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(0), a(1), sel(0), im0);
m2: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(2), a(3), sel(0), im1);
m3: ENTITY WORK.Mux2x1(selected) PORT MAP (im0, im1, sel(1), z);
END mux2x1_based;

VHDL Code for a 2:1 MUX

library IEEE;
use ieee.std_logic_1164.all;

ENTITY Mux2x1 IS {
PORT (a0, a1, sel: IN BIT; z: OUT BIT); }
END Mux2x1;

ARCHITECTURE conditional OF Mux2x1 IS
BEGIN
z <= a0 WHEN sel = ‘0’ ELSE a1;
END conditional;

VHDL code for a Function

This example shows the VHDL code that you can use if you want to implement a function:
f= (xy'z)+(xyz')+(xyz)

library IEEE;
use ieee.std_logic_1164.all;

entity FUNCTIONEXAMPLE is port(
x: in std_logic;
y:in std_logic;
z: in std_logic;
f: out std_logic;
end FUNCTIONEXAMPLE;

architecture behav of FUNCTIONEXAMPLE is
signal term_1, term_2, term_3: std_logic;
begin
term_1 <= x AND (NOT y) AND z;
term_2 <= x AND y AND (NOT z);
term_3 <= x AND y AND z;
f <= term_1 OR term_2 OR term_3;
end behav;

VHDL code for 3 input NOR gate

library IEEE;
use IEEE.std_logic_1164.all;

entity NORGATE3 is port(
x: in std_logic;
y: in std_logic;
z: in std_logic;
f: out std_logic);
end NORGATE3;

architecture behav of NORGATE3 is
signal xory, xoryorz:std_logic;
begin
xory<= x OR y;
xoryorz <= xory OR z;
f<= NOT xoryorz;

end behav;

VHDL code for 2 input NAND gate

library ieee;
use ieee.std_logic_1164.all;

entity NANDGATE2 is port(
x: in std_logic;
y: in std_logic;
f: out std_logic);
end NANDGATE2;

architecture behav of NANDGATE2 is
begin
f<= x NAND y;
end behav;

VHDL code for Correct Clock (For instance UART Clock)

The next VHDL sample code shows you how to get an UART clock out of an 50Mhz clock (for i nstance on your Xilinx board). For getting 38,4Khz out of 50Mhz we have to divide the frequency by 130. 130 is in hexadecimal format 82. So in my VHDL code you see X"82" this means 130 in decimal format.

library IEEE;
use IEEE.std_logic_1164.all;

entity UART_CLK is
port(
clk: in std_logic;
rst: in std_logic;
CLK384: out std_logic
);
end UART_CLK;

architecture behav of UART_CLK is
signal clkDiv: std_logic_vector(7 downto 0);
signal CLKt: std_ulogic;
constant baudDivide: std_logic_vector (7 downto 0) :=X"82";

begin

process(clk,rst)
begin
if (rst='1') then
clkDiv <= baudDivide;
CLKt<='0';
elseif (clk='1' and clk'event) then
if (clkDiv=X"00") then
clkDiv<=baudDivide;
CLKt <=not CLKt;
else
clkDiv <=clkDiv -1;
end if;
end if
end process;
CLK384 <=CLKt;
end behav;

VHDL code for Rising edge D Flip-Flop with Asynchronous Reset

library IEEE;
use IEEE.std_logic_1164.all;

entity dff_async_rst is
port ( data, clk, reset: in std_logic;
q: out std_logic);
end dff_async_rst;

architecture behav of dff_async_rst is
begin
process (clk, reset) begin
if (reset = '0') then
q<='0';
elsif (clk'event and clk='1') then
q<= data;
end if;
end process
end behav;

VHDL code for Rising edge D Flip-Flop

library IEEE;
use IEEE.std_logic_1164.all;

entity dff is
port ( data,clk,: in std_logic;
q: out std_logic);
end dff;

architecture behav of dff is
begin
process (clk) begin
if (clk'event and clk='1') then
q <= data;
end if;
end process;
end behav;

VHDL reserved keywords

The following is a list of the VHDL reserved keywords:

• abs
• access
• after
• alias
• all
• and
• architecture
• array
• assert
• attribute
• begin
• block
• body
• buffer
• bus
• case
• component
• configuration
• constant
• disconnect
• downto
• else
• elsif
• end
• entity
• exit
• file
• for
• function
• generate
• generic
• group
• guarded
• if
• impure
• in
• inertial
• inout
• is
• label
• library
• linkage
• literal
• loop
• map
• mod
• nand
• new
• next
• nor
• not
• null
• of
• on
• open
• or
• others
• out
• package
• port
• postponed
• procedure
• process
• pure
• range
• record
• register
• reject
• rem
• report
• return
• rol
• ror
• select
• severity
• shared
• signal
• sla
• sra
• srl
• subtype
• then
• to
• transport
• type
• unaffected
• units
• until
• use
• variable
• wait
• when
• while
• with
• xnor
• xor